最近の発表論文

2024年

• Katsutoshi Otsuka, Kazuhito Ito, "Double Moduler Redundancy Design of LSI Controller for Soft Error Tolerance," Proc. Workshop on Synthesis and System Integration of Mixed Information Technologies, pp. 20-25, 2024.
• Kazuma Dobata, Kazuhito Ito, "Reduction of Static Power Consumption of LSI by Decreasing Leakage Current Paths with Equivalent Logic Expression Conversion," Proc. Workshop on Synthesis and System Integration of Mixed Information Technologies, pp. 299-304, 2024.

2023年

• 岸本拓人, 伊藤和人, LSI 設計における演算スケジューリングのイジングモデル定式化, 電子情報通信学会総合大会, pp. A-6-1, 2023年.
• 林伸幸, 伊藤和人, レジスタブリッジ型LSI の力学モデルによる演算マッピング, 電子情報通信学会総合大会, pp. A-6-2, 2023年.

2022年

• Mitsuru Takahashi, Kazuhito Ito, "An Efficient LSI Implementation of the Summation of Products in Convolution Operation for Binarized Neural Networks," Proc. Workshop on Synthesis and System Integration of Mixed Information Technologies, pp. 96-101, 2022.
• Yuki Imai, Shinichi Nishizawa, Kazuhito Ito, "Reduction of LSI Maximum Power Consumption with Standard Cell Library of Stack Structured Cells," IEICE Trans. Fundamentals, Vol. E105-A, No. 3, pp. 487-496, Mar. 2022.
• Yuya Kitazawa, Kazuhito Ito, "Register Minimization and its Application in Schedule Exploration for Area Minimization for Double Modular Redundancy LSI Design," IEICE Trans. Fundamentals, Vol. E105-A, No. 3, pp. 530-539, Mar. 2022.

2021年

• 新井正敏, 伊藤和人, "画像特徴点を使ったGUIシステムの自動実装検証の開発, システム制御情報学会論文誌, 第34巻, 第1号, pp. 23-25, 2021.

2020年

• Kazuhito Ito, "Energy Minimization of Double Modular Redundant Conditional Processing by Common Condition Dependency," IEICE Trans. Electron., Vol. E103-C, No. 4, pp. 181-185, 2020.

2019年

• Kota Chubachi, Shinichi Nishizawa, Kazuhito Ito, "Analog circuit design methodology utilizing a structure of thin BOX FDSOI," IEICE Electronics Express, Vol. 16, No. 5, pp. 20181136, 2019.
• Yuya Kitazawa, Shinichi Nishizaw, Kazuhito Ito, "Register Minimization in Double Modular Redundancy Design with Soft Error Correction by Replay," Proc. Workshop on Synthesis and System Integration of Mixed Information Technologies, pp. 192-197, 2019.
• Kazuhito Ito, "Minimization of Energy Consumption of Double Modular Redundancy Design of Conditional Processing by Common Condition Dependency," Proc. Workshop on Synthesis and System Integration of Mixed Information Technologies, pp. 18-23, 2019.

2018年

• Kazuhito Ito, Yuto Ishihara, Shinichi Nishizawa, "Minimization of Vote Operations for Soft Error Detection in DMR Design with Error Correction by Operation Re-Execution," IEICE Trans. Fundamentals, Vol. E101-A, No. 12, pp. 2271-2279, Dec. 2018.

2017年

• 石原裕人，西澤真一, 伊藤和人, 二重冗長化処理の誤り検出最少化スケジューリング手法，電子情報通信学会ソサイエティ大会, pp. A-1-7, 2017年.
• 伊藤和人, 二重冗長化処理におけるレジスタ面積コスト最小化, 電子情報通信学会ソサイエティ大会, pp. A-1-8, 2017年.
• 中鉢洸太, 西澤真一, 伊藤和人, 薄膜FDSOIトランジスタを用いた低電圧動作逆方向バイアス電圧生成回路, DAシンポジウム, 2017年.

2016年

• Hiroki Hayashi, Kazuhito Ito, "Hardware-Efficient Local Extrema Detection for Scale-Space Extrema Detection in SIFT Algorithm," IEICE Trans. Fundamentals, Vol. E99-A, No. 12, pp. 2507-2510, Dec. 2016.
• Kazuhito Ito, "Low Complexity Reed-Solomon Decoder Design with Pipelined Recursive Euclidean Algorithm," IEICE Trans. Fundamentals, Vol. E99-A, No. 12, pp. 2453-2462, Dec. 2016.
• Takafumi Fujii, Shinichi Nishizawa, Kazuhito Ito, "Register-Bridge Architecture and its Application to Multiprocessor Systems," Proc. Workshop on Synthesis and System Integration of Mixed Information Technologies, pp. 10-15, Oct. 2016.
• 中馬良兵, 西澤真一, 伊藤和人, 極低電圧動作を目指したD-Nwellレス細粒度基板バイアスSRAMビットセルの検討, DAシンポジウム, 2016年.
• 杉山方健, 西澤真一, 伊藤和人, GPGPUによるFPGA向けテクノロジマッピングの高速化, 電子情報通信学会総合大会, pp. A-6-2, 2016年.

2015年

• Kazuhito Ito, "A Low Power and Hardware Efficient Syndrome Key Equation Solver Architecture and Its Folding with Pipelining," IEICE Trans. Fundamentals, Vol. E98-A, No. 5, pp.1058-1066, 2015年.
• Kazuhito Ito, Takumi Negishi, "Minimization of Register Area Cost for Soft-Error Correction in Low Energy DMR Design," Proc. Workshop on Synthesis and System Integration of Mixed Information Technologies, pp. 56-61, March 2015.

2014年

• Kazuhito Ito, "Energy Minimization of Full TMR Design with Optimized Selection of Temporal/Spatial TMR Mode and Supply Voltage," IEICE Trans. Fundamentals, Vol. E97-A, No. 12, pp.2530-2539, 2014年.
• 伊藤和人, "乗算器数を削減した低電力シンドローム基本方程式求解手法," 電子情報通信学会2014年ソサイエティ大会講演論文集, A-3-4, 2014年9月.

2013年

• Kazuhito Ito, Ryoto Shirasaka, "Hardware Efficient and Low Latency Implementations of Look-Ahead ACS Computation for Viterbi Decoders," IEICE Trans. Fundamentals, Vol. E96-A, No. 12, pp.2680-2688, 2013年.
• Yusuke Ota, Kazuhito Ito, "A Parallel Simulated Annealing Algorithm with Look-Ahead Neighbor Solution Generation," Proc. Workshop on Synthesis and System Integration of Mixed Information Technologies, pp. 106-111, Oct. 2013.
• Kazuhito Ito, Yuki Hayashi, "A Low Energy Full TMR Design Method with Optimized Selection of Time/Space TMR Mode and Supply Voltage," Proc. Workshop on Synthesis and System Integration of Mixed Information Technologies, pp. 334-339, Oct. 2013.
• 伊藤和人, "低消費電力シンドローム基本方程式求解アーキテクチャ," 電子情報通信学会論文誌, Vol. J96-A, No.9, pp. 691-694, 2013年.
• 伊藤和人, 白坂龍人, 大西秀児, "高速ヴィタビ復号の先見ACS計算レイテンシ削減手法," 電子情報通信学会論文誌, Vol. J96-A, No.9, pp. 695-698, 2013年.
• Kazuhito Ito, Kazuhiko Kameda, "A Method to Reduce Energy Consumption of Conditional Operations with Execution Probabilities," IPSJ Trans. System Level Design Methodology, Vol. 6, pp.60-70, 2013.
• Kazuhito Ito, "Valid Digit and Overflow Information to Reduce Energy Dissipation of Functional Units in General Purpose Processors," IEICE Trans. Electronics, Vol. E96-C, No.4, pp.463-472, 2013.
• Kazuhito Ito, "An Area-Time Efficient Key Equation Solver with Euclidean Algorithm for Reed-Solomon Decoders," IEICE Trans. Fundamentals, Vol. E96-A, No. 2, pp. 609-617, 2013.

2012年

• 太田悠介, 伊藤和人, "先見近傍解生成による焼きなまし法の並列化手法," 電子情報通信学会技術報告, VLD2012-73, pp.81-86, 2012年11月.
• Kazuhito Ito, Keisuke Nasu, "A Processor Accelerator for Software Decoding of Reed- Solomon Codes," IEICE Trans. Fundamentals, Vol. E95-A, No.5, pp. 884-893, 2012.
• Kazuhito Ito, "A Trace-Back Method with Source States and its Application to Viterbi Decoders of Low Power and Short Latency," Proc. Workshop on Synthesis and System Integration of Mixed Information Technologies, pp. 372-377, March 2012.
• Yuki Suda, Kazuhito Ito, "A Method of Power Supply Voltage Assignment and Scheduling of Operations to Reduce Energy Consumption of Error Detectable Computations," Proc. Workshop on Synthesis and System Integration of Mixed Information Technologies, pp. 420-424, March 2012.
• Kazuhito Ito, "A Trace-Back Method with Source States for Viterbi Decoding of Rate-1/n Convolutional Codes," IEICE Trans. Fundamentals, Vol. E95-A, No.4, pp. 767-775, 2012.

2010年

• Kazuhito Ito, "A Processor Accelerator for Software Decoding of BCH Codes," IEICE Trans. Fundamentals, Vol. E38-A, No.7, pp. 1329-1337, 2010.
• Hidekazu Seto and Kazuhito Ito, "A Resource Binding Method to Reduce Data Communication Power Dissipation on LSI," IPSJ Trans. System Level Design Methodology, Vol. 3, pp. 257-267, 2010.

2009年

• Hidekazu Seto and K. Ito, "A Resource Binding Method to Reduce Data Communication Power Dissipation on LSI," 電子情報通信学会技術報告, VLD2009-45, pp.25-30, 2009年12月.
• K. Ito and Hyun-Joon Kim, "A Method to Reduce Power Dissipation of Conditional Operations with Execution Probabilities and its Application to Dual Supply Voltage System," 電子情報通信学会技術報告, VLD2009-44, pp.19-24, 2009年12月.
• K. Ito, Y. Nagasaka, "Energy Dissipation Reduction of Arithmetic Operations with Valid Digits," Proc. Workshop on Synthesis and System Integration of Mixed Information Technologies, pp. 35-40, 2009.